The design of the circuit architecture of an operational amplifier has been conventionally predicated upon a trade-off between high speed and (low frequency) precision performance. In the former case, the single stage, dominant pole, compensated operational amplifier is capable of achieving maximum possible speed for a given integrated circuit process, but lacks precision due to the limited impedance level that can be attained by a single transimpedance stage, as well as the offset errors induced by reflected mismatch errors from the level-shifting transimpedance and output buffer stage to the input transconductance stage. In the latter case, on the other hand, a two stage, `pole-splitting`, compensated operational amplifier, which is capable of high precision, lacks speed due to the inherent secondary pole, the right-half plane zero and the additional phase shift that results from the extra stage in the signal path.
Attempts to combine high speed and precision components into the same circuit architecture have involved the use of feed-forward techniques (by-pass capacitors) to circumvent the limitations of lateral pnp transistors of which the precision amplifier stage is typically comprised. This approach, however, introduces added complexity to the circuit design and AC coupling into the signal path. For an illustration of these conventional amplifier designs attention may be directed to published articles, such as "High-frequency, CMOS switched-capacitor filters for communications applications", by T.C. Choi et al, IEEE J. Solid-State Circuits, Vol. SC-18, pp. 652-664, Dec. 1983; "An interated NMOS operational amplifier with internal compensation", by Y.P. Tsividis et al, IEEE J. Solid-State Circuits, Vol. SC-11, No. 6, pp. 748-753, Dec. 1976; and "A monolithic fast settling feed-forward op amp using doublet compensation techniques", by R.J. Apfel et al, ISSCC Dig. Tech. Papers, 1974, pp. 134-134.